Field of the Invention
The invention relates to a successive approximation register for an analog/digital converter operating according to the weighing method (digit at a time) and having a bit width n, including memory elements each having one data input and one data output for shifting onward a logical "1" potential for each successive weighing step as well as for writing-in and storing in memory the particular result of weighing ascertained by a comparator.
Registers of this kind are used primarily in analog/digital converters operating according to the weighing method. In this conversion method, the digit places in the register are set successively to a logical "1" potential, beginning with the most significant bit and they are monitored as to whether or not the input voltage is higher than the voltage that corresponds to the digital word of the successive approximation register. If that is the case, then it remains set, but otherwise it is erased. This weighing process is repeated for each bit until the least significant bit is also defined at the end of the conversion phase.
The analog/digital conversion is controlled through the successive approximation register. An analog/digital converter of this kind is described, for instance, in the book entitled "Halbleiter-Schaltungstechnik" [Semiconductor Circuit Technology] by U. Tietze and Ch. Schenk, 7th revised edition, Springer-Verlag, Berlin, Heidelberg, New York, 1985, page 767, in particular pages 769 et seq.
The successive approximation register includes a shift register, in which the a logical "1" potential is incremented by one position at each clock pulse. As a result, the bits are set empirically, in order, to the logical "1" potential. The result of a particular weighing process is also stored in memory elements, into which the applicable comparator state is read. Only the memory element having the associated bit which has just been tested, is made available in this process. Accordingly, for the conversion phase, twice as many memory elements are required as there are bits.
Once the least significant bit has been defined, a further memory element of the shift register is typically set, in order to indicate that the conversion phase has been completed.
It is accordingly an object of the invention to provide a successive approximation register, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type, which performs its function with the lowest possible number of memory elements and which in particular can be implemented in simple fashion for integrated MOS technology.